Solder in cavity interconnection structures

ABSTRACT

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a divisional of U.S. patent application Ser.No. 14/643,329, filed Mar. 10, 2015, which is a continuation of U.S.patent application Ser. No. 13/740,698, filed Jan. 14, 2014, now U.S.Pat. No. 9,006,890 issued Apr. 14, 2015, which is a divisional of U.S.patent application Ser. No. 13/069,601, filed Mar. 23, 2011, now U.S.Pat. No. 8,936,967 issued Jan. 20, 2015.

BACKGROUND

A typical microelectronic package includes at least one substrate, suchas a microelectronic die, that is mounted to another substrate, such asan interposer or a printed circuit board, wherein bond pads on onesubstrate are attached to corresponding contact lands on the othersubstrate using reflowable solder materials.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter of the present disclosure is particularly pointed outand distinctly claimed in the concluding portion of the specification.The foregoing and other features of the present disclosure will becomemore fully apparent from the following description and appended claims,taken in conjunction with the accompanying drawings. It is understoodthat the accompanying drawings depict only several embodiments inaccordance with the present disclosure and are, therefore, not to beconsidered limiting of its scope. The disclosure will be described withadditional specificity and detail through use of the accompanyingdrawings, such that the advantages of the present disclosure can be morereadily ascertained, in which:

FIGS. 1-4 illustrate side cross-sectional views of a process of forminga cavity structure, according to one embodiment of the presentdisclosure.

FIG. 5 is a flow diagram of a process of forming a solder in cavityinterconnection structure, according to the present disclosure.

FIGS. 6-9 illustrate side cross-sectional views of a process of forminga solder in cavity interconnection structure, according to oneembodiment of the present disclosure.

FIGS. 10-12 illustrate side cross-sectional views of a process offorming a solder in cavity interconnection structure, according toanother embodiment of the present disclosure.

FIG. 13 illustrates a side cross-sectional view of still anotherembodiment of forming a solder in cavity interconnection structure,according to the present disclosure.

FIG. 14 illustrates a side cross-sectional view of an embodiment offorming a solder in cavity interconnection structure utilizing anunderfill material, according to the present disclosure.

FIG. 15 illustrates a side cross-sectional view of another embodiment offorming a solder in cavity interconnection structure utilizing anunderfill material, according to the present disclosure.

FIG. 16 is a flow diagram of a process of forming a solder in cavityinterconnection structure, according to the present disclosure.

FIGS. 17-20 illustrate side cross-sectional views of a process offorming a solder in cavity interconnection structure, according to stillanother embodiment of the present disclosure.

FIGS. 21 and 22 illustrate side cross-sectional views of a process offorming a solder in cavity interconnection structure, according to yetstill another embodiment of the present disclosure.

FIG. 23 is a flow diagram of a process of forming a solder in cavityinterconnection structure, according to an embodiment of the presentdisclosure.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the claimed subject matter may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the subject matter. It is to be understood thatthe various embodiments, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein, in connection with one embodiment, maybe implemented within other embodiments without departing from thespirit and scope of the claimed subject matter. References within thisspecification to “one embodiment” or “an embodiment” mean that aparticular feature, structure, or characteristic described in connectionwith the embodiment is included in at least one implementationencompassed within the present invention. Therefore, the use of thephrase “one embodiment” or “in an embodiment” does not necessarily referto the same embodiment. In addition, it is to be understood that thelocation or arrangement of individual elements within each disclosedembodiment may be modified without departing from the spirit and scopeof the claimed subject matter. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thesubject matter is defined only by the appended claims, appropriatelyinterpreted, along with the full range of equivalents to which theappended claims are entitled. In the drawings, like numerals refer tothe same or similar elements or functionality throughout the severalviews, and that elements depicted therein are not necessarily to scalewith one another, rather individual elements may be enlarged or reducedin order to more easily comprehend the elements in the context of thepresent description.

Embodiments of the present description relate to the field offabricating microelectronic packages, wherein cavities are formed in adielectric layer deposited on a first substrate to maintain separationbetween soldered interconnections. In one embodiment, the cavities mayhave sloped sidewalls. In another embodiment, a solder paste may bedeposited in the cavities and upon heating solder structures may beformed. In other embodiments, the solder structures may be placed in thecavities or may be formed on a second substrate to which the firstsubstrate may be connected. In still other embodiments, solderstructures may be formed on both the first substrate and a secondsubstrate. The solder structures may be used to form solderinterconnects by contact and reflow with either contact lands or solderstructures on a second substrate. In some cases, the cavities can reducebridging or cracking failures of the solder connections, and may permitsmaller interconnection pitch. Additionally, in some cases, thereliability of the connections may be improved. Furthermore, the wallsof the cavities may be used to strengthen or support the solder joints,particularly in response to lateral loading.

In the production of microelectronic packages, microelectronic dice aregenerally mounted on substrates that may, in turn, be mounted to boards,which provide electrical communication routes between themicroelectronic dice and external components. A microelectronic die,such as a microprocessor, a chipset, a graphics device, a wirelessdevice, a memory device, an application specific integrated circuit, orthe like, may be attached to a substrate, such as an interposer, amotherboard, and the like, through a plurality of interconnects, such asreflowable solder bumps or balls, in a configuration generally known asa flip-chip or controlled collapse chip connection (“C4”) configuration.When the microelectronic die is attached to the substrate withinterconnects made of solder, the solder is reflowed (i.e. heated) tosecure the solder between the microelectronic die bond pads and thesubstrate bond pads. The microelectronic die may also be attached with athermo-compression bonding process to form an interconnection between anattachment structure of the microelectronic die and the substrate bondpad, as will be understood to those skilled in the art.

While C4 connections have been widely utilized in the microelectronicindustry; there is a continuing desire to increase the density ofinterconnections that can be formed. The more interconnections per unitof area that can be formed, the smaller the resulting microelectronicdevices can be. In general, the smaller the microelectronic device, thelower their cost and the greater their performance.

FIGS. 1-9 illustrate an embodiment of forming a microelectronicstructure according to at least one embodiment of the presentdisclosure. FIG. 1 shows a first substrate 102, which may include anintegrated circuit wafer, a printed circuit board, an interposer, amicroelectronic die, or a microelectronic device package. The firstsubstrate 102 may include at least one attachment structure, such as aplurality of bond pads 104 adjacent a contact surface 106 thereof. Thefirst substrate bond pads 104 may be any appropriate conductivematerial, including but not limited to copper, aluminum, nickel, silver,and alloys thereof, and may be in electric communication with integratedcircuits, contacts, traces, and/or the like (not shown) within the firstsubstrate 102, as will be understood to those skilled in the art.

As shown in FIG. 2, a dielectric layer 112 may be formed over the firstsubstrate bond pads 104 and the first substrate contact surface 106. Inone embodiment, the dielectric layer 112 may include, but is not limitedto, a photo-definable layer or a dry film. In one embodiment, thedielectric layer 112 may be a negative tone chemically amplifiedphotoresist, which can be epoxy-based, novolak-based, polyimide-based,or the like. The dielectric layer 112 may be formed by any techniqueknown in the art, including but not limited to imprinting, pasteprinting, laminating, and spin coating.

As shown in FIG. 3, cavities 114 may be formed through the dielectriclayer 112 which expose at least portion of each first substrate bondpads 104, as shown in FIG. 3. As further shown in FIG. 3, the cavities114 may be directly adjacent to one another. In one embodiment, thecavities 114 may be formed the dielectric layer 112 by any knowntechniques, including but not limited to patterning and etching with alithography technique. As a result of forming the cavities 114,intervening inter-cavity walls 116 are formed between the cavities 114from the remaining dielectric layer 112 (see FIG. 2).

As still further shown in FIG. 3, one embodiment of the presentdisclosure the inter-cavity walls 116 may be defined by sloped sidewalls122, such that the cavities 114 are wider at an outer surface 118 of thedielectric layer 112 (see FIG. 2) than proximate the first substratebond pads 104. In one embodiment of the present description, thesidewalls may have an angle α of between about 10 and 60 degrees fromperpendicular from the first substrate contact surface 106. In anembodiment, the cavities 114 may be substantially conical, such as thetruncated conical shape shown in FIG. 4.

FIG. 5 illustrates a flow diagram of one process 200 of forming slopedsidewalls 122 of the present application. As shown in block 210, adielectric layer, such as a negative tone chemically amplifiedphotoresist, may be formed with a carrier solvent on a substrate. Thesolvent may be removed in a soft bake, usually between about 90 and 100degrees C., as shown in block 220. As shown in block 230, the dielectriclayer may be exposed to form a desired pattern, such as by a standardlithographic techniques. As shown in block 240, a post exposure bake maybe performed by placing the substrate on a heated surface. By using aheated surface and by tuning the post exposure bake temperature andduration, it may be possible to create a gradient in cross-link densityand/or number that may substantially correspond to the thermal gradientacross the substrate. For example, when the dielectric material is aresist material, the dielectric material closest to the heated surfacecan become more cross-linked and/or a photo-acid within the dielectricmaterial diffuses into areas that are not exposed and continuescross-linking while the dielectric material farthest away from theheated surface can become less cross-linked or the diffusion of thephoto-acid is limited. As shown in block 250, the dielectric layerdevelopment may be completed, which includes curing the electricmaterial and removing dielectric material to form the cavities. In oneembodiment, due to the densification and/or diffusion gradient ofphoto-acid, it is possible to form sloped sidewalls in the cavities uponthe development of the dielectric material. In other words, moredielectric material is removed from the top of the dielectric layer,while less material is removed from the dielectric material closest tothe heated surface. As shown in block 260, an optional hard bake may beperformed. In another embodiment, the cross-link density, the shrinkageof the dielectric material, and the coefficient of thermal expansion maybe modulated by adjusting the ramp rate to and the magnitude of the hightemperature cure. This may be particular applicable to polyimide-basedmaterials, which can exhibit shrinkage of greater than 10%.Consequently, the greater the shrinkage or the higher the coefficient ofthermal expansion, the larger the contraction. Thus, when a thickdielectric layer is patterned to have perpendicular sidewalls, thedielectric material in contact with the rigid substrate exhibits thepatterned opening critical dimension while the dielectric materialfurthest from the substrate contracts unconstrained and forms a wideopening, which results in sloped sidewalls.

As shown in FIG. 6, the cavities 114 (see FIG. 3) may act as a mold forprinting of solder paste 124, wherein the solder paste 124 is depositedwithin the cavities 114 (see FIG. 3). Any known technique for depositingthe solder paste 124 may be utilized, as will be understood to thoseskilled in the art. The solder paste 124 may be any known solder paste,including, but not limited to micro-balls of solder powder dispersed ina flux matrix.

As shown in FIG. 7, the solder paste 124 (see FIG. 5) is heated to aboutits melting temperature, referred to as “reflow”. This results in thesolder paste 124 substantially taking on a hemispherical shape, referredto as a solder ball (shown in FIG. 7) or forming a curved structure witha flattened surface adjacent to the first substrate bond pad 104 (shownin FIG. 18). These spheres and curved structures will be collectivelyreferred to as “solder structures 126”. The shape taken on by the solderstructures 126 is dependent, at least in part, by the cohesive force ofthe solder material itself and by the surface energy between the soldermaterial and the first substrate bond pad 104. During the reflowprocess, the flux matrix within the solder paste 124 may be volatized toleave solder material behind, which forms the solder structures 126.Thus, the volume of the solder paste 124 will be greater than the volumeof the solder structures 126. Therefore, the slope in the sidewalls 122may also allow for an appropriate volume of solder paste 124 to form adesired solder structure 126 size.

The solder structures 126 may be any appropriate material, including butnot limited to lead/tin alloys, such as tin/lead solder, such as 63%tin/37% lead solder, or lead-free solders, such a pure tin or high tincontent alloys (e.g. 90% or more tin), such as tin/bismuth, eutectictin/silver, ternary tin/silver/copper, eutectic tin/copper, and similaralloys.

It is understood that the solder structures 126 could be placed in thecavities 114 by microball printing, thereby by-passing the solder pasteprinting and reflowing processes to form the solder structures 126,previously described.

As shown in FIG. 8, the solder structures 126 of the first substrate 102may be brought into contact with contact lands 134 proximate a contactsurface 136 of a second substrate 132, wherein the pattern ordistribution of the second substrate contact lands 134 may be asubstantial mirror-image to the pattern or distribution of the firstsubstrate bond pads 104. The second substrate 132 may be, but is notlimited to, an integrated circuit wafer, a printed circuit board, aninterposer, a microelectronic die, a microelectronic device package, orthe like. The second substrate contact lands 134 may be any appropriateconductive material, including but not limited to copper, aluminum,nickel, silver, and alloys thereof, and may be in electric communicationwith integrated circuits, contacts, traces, and/or the like (not shown)within the second substrate 132, as will be understood to those skilledin the art.

As shown in FIG. 9, in one embodiment, the solder structures 126 may besubstantially heated to their reflow temperature, then cooled toresolidify, thereby forming a solder interconnects 138 between the firstsubstrate bond pads 104 and the second substrate contact lands 134,which attaches the first substrate 102 to the second substrate 132. Inanother embodiment, thermal compression bonding (e.g. pressure and heat)may be used to form the solder interconnects 138 and attach the firstsubstrate 102 to the second substrate 132, as will be understood tothose skilled in the art.

In another embodiment of the present description illustrated in FIG. 10,the first substrate 102 may be formed with the bond pads 104 adjacentthe first substrate contact surface 106, as previously described. Thedielectric layer 112 may be formed over the first substrate contactsurface 106, then patterned and etched to form the cavities 114. Thecavities 114 may be formed such that the intervening inter-cavity walls116 have sloped sidewalls 122, as previously discussed. The interveninginter-cavities walls 116 may also include contact structures 142 formedbetween each of the adjacent cavities 114, wherein the inter-cavity wallcontact surfaces 142 may be substantially planar to the first substratecontact surface 106.

As shown in FIG. 11, solder structures 126 may be formed within thecavities 114 in a manner or manners previously discussed, wherein thesolder structures 126 may be contained completely within the cavities114. As further shown in FIG. 11, the solder structures 126 of the firstsubstrate 102 may be aligned with the contact lands 134 on a secondsubstrate 132, wherein the contact surfaces 142 of the interveninginter-cavities walls 116 contact the second substrate contact surface136.

When the attachment process is performed, such as reflow or thermalcompressive bonding, the dielectric material 112 deforms tosubstantially fill gaps 152 (see FIG. 11) between the solderinterconnections 138 and the inter-cavity walls 116, as shown in FIG.12. In one embodiment, the dielectric material of the inter-cavity walls116 is sufficiently deformable to substantially fill the gaps 152 (seeFIG. 11) between the solder interconnections 138 and the dielectricmaterial 112. In another embodiment, the dielectric material of theinter-cavity walls 116 may flow during the attachment process (e.g. whenheat is applied) to substantially fill the gaps 152 (see FIG. 11)between the solder interconnections 138 and the inter-cavity walls 116.

In another embodiment shown in FIG. 13, the solder structure 126 may beformed on the second substrate contact lands 134 by any technique knownin the art. After the attachment process, a structure similar to thestructures shown in FIG. 9 or FIG. 12 may be formed.

In still another embodiment shown in FIG. 14, the embodiment of FIG. 13may have an underfill material 162, such as an epoxy material (with orwithout flux) or a no-flow underfill (NFU) material, deposited over thesecond substrate contact surface 136, a portion of the second substratecontact lands 134, and the solder structures 126. The underfill material162 may assist in filling any voids 152 between the dielectric layer 112and the solder interconnections 136 (see FIG. 11).

In another embodiment shown in FIG. 15, the underfill material 162 maybe deposited over the second substrate contact surface 136 and thesecond substrate contact lands 134 for embodiments, such as shown inFIGS. 1-12. The underfill material 162 may fill space between the firstsubstrate 102 and the second substrate 132 (see FIG. 8) or may assist infilling any voids between the dielectric layer 112 and the solderinterconnections 136 (see FIGS. 9 and 11).

An embodiment of a process of the present description is illustrated inthe flow diagram 300 of FIG. 16. As defined in block 310, a firstsubstrate may be formed with bond pads proximate a contact surfacethereof. A dielectric layer may be formed over the first substrate bondpads and the first substrate contact surface, as defined in block 320.As defined in block 330, cavities may be formed through the dielectriclayer to expose at least a portion of each first substrate bond pad,wherein the sidewalls of the cavities are sloped, such that the cavitiesare wider at an outer surface of the dielectric layer than proximate thefirst substrate bond pads. As defined in block 340, a second substratemay be formed with contact lands proximate a contact surface of thesecond substrate. As defined in block 350, solder structures may beformed on at least one of the first substrate bonds and the secondsubstrate contact lands. As defined in block 360, solderinterconnections may be formed from the solder structures between thefirst substrate bond pads and the second substrate contact lands.

In one embodiment illustrated in FIGS. 17-20, the interconnectionstructures may be formed from first solder structures 402 on the firstsubstrate 102 and second solder structures 412 on the second substrate132. As shown in FIG. 17, the first solder structures 402 are formed incavities 114 in a first dielectric layer 404 in a manner previouslydiscussed. It is noted that the inter-cavity wall sidewalls 122 for thecavities 114 are show as substantially perpendicular to the firstsubstrate contact surface 106; however, they may be formed to be sloped,as previously discussed. The second solder structures 412 may be formedon the contact lands 134 on the contact surface 136 of the secondsubstrate 132. The second solder structures 412 may be formed by forminga second dielectric layer 414, such as a solder mask photoresistmaterial, on second substrate contact surface 136. The second dielectriclayer 414 may be patterned and etched to form openings 416 to expose atleast portion of each of the second substrate contact lands 134. Thesecond solder structures 412 may then be formed in the openings 416 byany known technique, including as those which have been previouslydiscussed. It is noted that sidewalls 418 for the openings 416 are showas substantially perpendicular to the second substrate contact surface136; however, they may be formed to be sloped, as previously discussed.

As shown in FIG. 18, an underfill material 422 may be de deposited overthe second dielectric layer 414 and the second solder structures 412.The first solder structures 402 may then be brought into contact withtheir corresponding second solder structures 412 and attached to oneanother by any known technique, including but not limited to reflow orthermal compression bonding, to form solder interconnections 420, asshown in FIG. 19. The underfill material 422 may flow to fill any voidsbetween the solder interconnections 420 and the first dielectric layer404, between the solder interconnections 420 and the second dielectriclayer 414, and between the first dielectric layer 404 and the seconddielectric layer 414, as shown in FIG. 20.

In one embodiment illustrated in FIGS. 21 and 22, the second solderstructures 412 may be formed on the second substrate contact lands 134with the second dielectric 414 (see FIG. 17) not used or having beenremoved. In this embodiment, the inter-cavity walls 116 of the firstdielectric layer 404 may have contact surfaces 424 formed between eachof the adjacent cavities 114 which may be substantially planar to thefirst substrate contact surface 106, such as previously discussed withregard to the embodiment illustrated in FIG. 11. As shown in FIG. 22,the first solder structures 402 may be aligned with the second solderstructures 404, wherein the contact surfaces 424 of the interveninginter-cavities walls 116 contact the second substrate contact surface136. The first solder structures 402 and corresponding second solderstructures 412 may be attached to one another to form interconnects 420by any known technique, including but not limited to reflow or thermalcompression bonding, as further shown in FIG. 22. It is understood thatan underfill material could be used, such as shown in FIGS. 18-20 tofill voids and provides a more robust package, as previously discussed.

An embodiment of a process of the present description is illustrated inthe flow diagram 500 of FIG. 23. As shown in block 510, a firstsubstrate may be formed with bond pads proximate a first surfacethereof. A first dielectric layer may be formed over the first substratebond pads and the first substrate contact surface, as defined in block520. As defined in block 530, cavities may be formed through the firstdielectric layer to expose at least a portion of each first substratebond pad. First solder structures may be formed on the first substratebond pads, as defined in block 540. As defined in block 550, a secondsubstrate may be formed with contact lands proximate a contact surfaceof the second substrate. As defined in block 560, second solderstructures may be formed on the contact lands on the contact surface ofthe second substrate. As defined in block 570, the first solderstructures may be brought into contact with the second solder structuresand adhered together to from interconnection structures.

Although the described embodiments within this description are directedto a first substrate and a second substrate, it is understood that theconcepts apply equally to any microelectronic packaging process,including but not limited to First Level Interconnects (FLI) wheremicroelectronic dice are attached to substrates or interposers, toSecond Level Interconnects (SLI) where substrates or interposers areattached to a board or a motherboard, and to Direct Chip Attach (DCA)where microelectronic dice are attached directly to a board or amotherboard.

Having thus described in detail embodiments of the present invention, itis understood that the invention defined by the appended claims is notto be limited by particular details set forth in the above description,as many apparent variations thereof are possible without departing fromthe spirit or scope thereof.

What is claimed is:
 1. A microelectronic device, comprising: a firstsubstrate having a contact surface comprising a plurality of bond pads;a dielectric structure disposed on the contact surface of the firstsubstrate, wherein the first dielectric structure has a plurality ofcavities extending therethrough to each of the plurality of firstsubstrate bond pads, wherein the cavities of the plurality of cavitieshave a substantially frustoconical shape, and wherein an intercavitysection of the first dielectric layer that is between two adjacentcavities of the plurality of cavities, comprises a first and a secondsurface that are substantially planar and are parallel to the contactsurface of the first substrate; a second substrate having a surfacecomprising a plurality of contact lands; and solder interconnectionsbetween the plurality of first substrate bond pads and correspondingsecond substrate contact lands of the plurality of second substratecontact lands.
 2. The microelectronic device of claim 1, wherein theplurality of cavities are narrower at a first end that is closest to thecontact surface of the first substrate and wider at a second end that isfurthest from the contact surface of the first substrate.
 3. Themicroelectronic device of claim 1, further including an underfillmaterial between the first substrate and the second substrate.
 4. Themicroelectronic device of claim 1, wherein the inter-cavity walls aredeformable.
 5. The microelectronic device of claim 1, wherein amicroelectronic die is operably coupled to the first substrate.
 6. Themicroelectronic device of claim 1, wherein the second substrate is amicroelectronic device package.